QS1RT VERB (VErsatile Radio Board) Project: (Click on picture above for a larger version) ADC: Linear Technology LTC2208 DAC: Analog Devices AD9744 CODEC: TI TLV320AIC23B FPGA: Altera EP3C25-QFP240 Cyclone III CPLD: Altera EMP240-QFP100 MAX II USB: Cypress CY7C68013A FX2 SERDES: TI TLK2701 EEPROM: Microchip 24C128 Internal encode clock is 125 MHz. Board interface is through: USB 2.0 or, Optic Fiber SFP Module at 2.5 Gbps or, Copper Cat6 cable at 2.5 Gbps. TI CODEC provides 48/96kHz audio in and audio out FPGA can be programmed via USB or Fiber/Copper interface in Fast Parallel Programming mode (byte wide transfers per clock cycle). JTAG interface for FPGA and CPLD Connectors: ADC IN DAC OUT EXT ENCODE IN MIC IN L&R AMPLIFIED AUDIO OUT L&R LINE IN L&R LINE OUT DC POWER IN JTAG USB 2.0 RJ45 (2.5 Gbps serial over copper) SFP (2.5 Gbps serial over fiber) TTL Level Serial from FX2 SPI and I2C to RF external RF board Statu