Wednesday, October 25, 2006

A SDR based on some K2 design ideas

Here is a diagram of a SDR that uses ideas from the K2 RF front end and PLL synthesizer:


It would use the K2's RF front end. I would substitute the TUF-1 mixer of the K2 with a switching mixer based on a FST3125 bus switch. The QSD would be at a fixed IF of 5 MHz. The LO for the QSD would be derived from a fixed 20 MHz oscillator divided by 4 to generate the quadrature signals needed to driver the QSD switches. The K2's PLL would be modified by eliminating the variable reference oscillator (resulting in the PLL tuning in 5 kHz steps) and substituting one of the LMX National PLLs for the MC145170 PLL used in the K2 design. The K2's VCO design is good, but I would also eliminate the VCO AGC circuit of the K2.

Tuesday, October 24, 2006

SDR LO Ideas

SDR LO Ideas:

There has been a lot of discussion of using DDS or PLLs for the LO generation for HPSDR and SoftRock like receivers. In the current SoftRock series the LO is generated by a crystal oscillator. The downsides of the above approaches are:

1. DDS: spurs and cost of a decent low jitter/low noise clock source. Some of the 400 and 500 MHz DDS chips are on the expensive side.

2. PLL: phase noise. A scheme using a microwave VCO/PLL and dividing it down into the HF range has been discussed. The latest feeling is that the phase noise reduction even after dividing down is not enough to provide a high performance system. A dual PLL loop approach has been proposed to improve phase noise performance but it is likely to be expensive. There are also PLL/DDS approaches of varying complexity.

3. Xtal: limited frequency agility, you are limited to tuning within the passband of your computer sound card.

There is a forth method that might work for lower cost SDR circuits like the SoftRock. It involves the method used for many years in which a VFO is mixed with a crystal oscillator. It is not hard to make a pretty stable and low noise VFO. The output of the VFO/Xtal oscillator could be fed into a microprocessor (like Microchip PIC18F2455/2550/4455/4550 series) or a FPGA/CPLD. The microprocessor or FPGA/CPLD would count the frequency of the VFO/Xtal oscillator and feed the frequency information to the PC for display in one of the SDR programs like PowerSDR or Rocky. This way you would have an indication of your true operating frequency as well as a real tuning knob that is coupled to the VFO (like a real radio!).

Since there is already a microprocessor or FPGA/CPLD involved in measuring the LO frequency and transmitting that information to the PC, VFO stabilization (like Huff-n-Puff techniques) could be also done in the microprocessor or FPGA/CPLD to tame drift in the VFO. This scheme would also work well for the real sampler with AD7760 I describe in the previous blog or when the ADC is integrated on the QSD board when eliminating the sound card. The frequency information would be transmitted to the PC over USB like the audio stream.

In the case where you would want to use the PC sound card but transmit the frequency of the VFO/Xtal oscillator to the PC, provisions could be made in the USB PIC (or you could use a FTDI chip) to control the bandpass filters also.

Tuesday, October 17, 2006

Possible QSD/ISD Switches/ ADC Idea/Misc

QSD/ISD Switches:

Here is a link the PDF data sheets of analog switches that can be investigated for use in QSD/ISD circuits:

Interesting ADC:

Here is a link to an interesting ADC by Analog Devices:

It is a 24 bit, 2.5 MSPS ADC. Here is the circuit idea:

It uses 1/2 of a QSD (not quadrature sampled) to mix the frequency band of interest down to zero Hz with a bandwidth of something like 250 kHz. The IF would be offset to something like 125 kHz. The ADC samples the 1/2QSD output and results in a real data stream. A FPGA or CPLD mixes the real data stream with a complex NCO to generate a quadrature data stream which is sent over USB to the PC where the remaining processing is done. The advantage is a 1 X LO and no I/Q balance problems. One disadvantage is that your sampling rate should be 4 times the desired bandwidth. For narrow band applications this should be no problem because the AD7760 will sample up to 2.5MSPS. A 500 MSPS rate into the PC should allow a bandwidth of almost +/- 125 kHz from the LO frequency.

Nice SDR Enclosure?

Ken N9VV sent me a link to a cool PC case: