Tuesday, October 30, 2007

QS1R REVB Picture

http://www.philcovington.com/SDR/PICS/qs1rt_revb.jpg

History of HPSDR Mercury and Quick Silver

History of HPSDR Mercury and Quick Silver

Philip Covington, N8VB

Early HPSDR and XYLO

In 2005 I started a High Performance SDR (HPSDR) project which was to consist of a motherboard carrying a FPGA/USB 2.0 interface and power supply with the provision for plug in modules through 40 pin headers. I had planned a narrow band high dynamic range module based on a QSD/DDS/PCM4202 audio ADC and a wide bandwidth module based on a high speed 16 bit ADC:

http://www.philcovington.com/SDR/PICS/HPSDR_FPGA_USB_Board_top1_800600.jpg

http://www.philcovington.com/SDR/PICS/HPSDR_FPGA_USB_Board_top4.jpg

I soon selected the LTC2208 ADC from Linear Technology. A representative from Linear Technology came across my blog (http://pcovington.blogspot.com/ ) and offered evaluation boards and samples to support the project.

At about the same time my HPSDR project came about, Phil Harman, VK6APH and Bill Tracey, KD5TFD were interested developing a sound card replacement to be used with the SDR-1000 and had started developing with a FPGA development board (XYLO) that had a high speed USB 2.0 interface. They formed the XYLO SDR group to support this. In March 2006, Phil Harman proposed that we merge my HPSDR project and XYLO SDR group into a common project since our goals were similar. By the middle of March 2006 an announcement was made that the groups would merge and the HPSDR.org website was set up.

HPSDR ATLAS and OZY

One of the first tasks was to define a backplane since various backplanes, such as passive PCI, were being proposed. I volunteered for the task which became the ATLAS backplane:

http://www.philcovington.com/HPSDR/ATLAS/REVA/atlas_1_REVA_BW.pdf

http://www.philcovington.com/HPSDR/ATLAS/ALPHA/Atlas_assy.pdf

We had an early volunteer to design an ATLAS plug-in FPGA/USB board to replace the XYLO board, but unfortunately the volunteer was not able to follow through with the task. I agreed to do the design for this board which became the HPSDR OZY board and to provide for the possibility of controlling a SDR-1000 through the OZY’s IO ports that simulate a PC parallel port:

http://www.philcovington.com/SDR/OZYREVA.jpg

Early HPSDR Mercury

Soon after the OZY design was done I began to pursue Mercury. I initially used the Linear Technology supplied evaluation board for the LTC2208. In May of 2006 I became very busy with a work project so I asked Phil Harman if he would like me to send him one of my LTC2208 evaluation boards to play with. I also sent Phil a Crystek low phase noise crystal oscillator that I had chosen as a candidate for driving the encode clock of the LTC2208 ADC. In the link below you can see the Mercury breadboard connected to the OZY. The LTC2208 evaluation board can be seen plugged in vertically to the breadboard with the RG 174/U cable running to the top of it:

http://hpsdr.org/wiki/index.php?title=Image:OZY_MERC_TEST.JPG

Quick Silver Version 1

In late 2006 I decided to design a board that I called Quick Silver (related to Mercury) which would become the initial prototype for HPSDR Mercury:

http://www.philcovington.com/SDR/PICS/QS1R_proto.JPG

http://www.philcovington.com/SDR/QS1RA_12012006.pdf

The initial thought about the design of HPSDR Mercury was that it would use either an Analog Devices AD6636 or AD6620 Digital Receive Signal Processor chip. The ADC6636 was only available in BGA packaging so I chose to use two AD6620 DDCs on the Quick Silver (also called QS1R REV AB). I wanted to investigate whether the AD6620/6636 was suitable for use with the LTC2208 in a HF receiver and also to test the choice of low noise Crystek oscillator encode circuitry which would be critical in determining the LTC2208 ADC’s performance.

It quickly became clear that the AD6620/6636 devices were not suitable from a dynamic range perspective for use in the HPSDR Mercury. About 90% of the DDC functionality was moved from the AD6620 into the Cyclone II FPGA on the QS1R REV AB prototype. There was not enough room in the FPGA to implement a useful final FIR compensating filter to correct for the passband droop of the CIC filters used in the FPGA implemented DDC. I then investigated using two external FIR filter chips made by a company called QuickFilter Technologies:

http://www.quickfiltertech.com/files/QF1D512%20SavFIRe%20Datasheet.pdf

Two of these chips were soon grafted on the QS1R board in place of the AD6620 parts for testing. These chips worked very well but I was concerned about their availability. I made a decision at that point to “bite the bullet” and wrote a one-tap-per-clock FIR filter in Verilog to move all of the DDC functionality into the FPGA. I was easily able to fit two 256 tap FIR filters into the remaining space in the Cyclone II FPGA which eliminated the need for the external QuickFilter FIR chips. During this time Altera also announced the availability of the Cyclone III FPGA in a QFP240 package with enough logical elements and hardware multipliers to be very interesting to SDR work – this also prompted me to develop the one-tap-per-clock FIR filter in Verilog since space would no longer be a concern with this FPGA.

The QS1R REV AB prototype allowed me to also test a Hittite HMC472 0-31.5 dB attenuator, a Sirenza SBF-4089/5089 RF Amp, Phil Harman’s 1.5 MHz BPF stage, and a 30/60 MHz LPF stage that is planned to be used in the HPSDR Mercury design.

The Quick Silver was the testing grounds for ideas that will be used in HPDSR Mercury. Without experience gained from the QS1R REV AB prototype, we would have probably ended up with multiple alpha releases of the Mercury as we found these problems later.

Quick Silver QS1RT VERB

During the development and testing of the QS1R REV AB prototype, the Altera Cyclone III FPGA became available in a QFP240 package with enough logical elements to do some interesting SDR work. I wanted to investigate using a PCI or PCIe connection to the PC to allow much wider bandwidths to be processed than the USB 2.0 interface would allow. This is how QS1RT VERB came about. The VERB contains both the LTC2208 ADC and a TxDAC with a fiber optic or copper connection to a PCI/PCIe board in a PC. The high speed serial interface between the QS1RT and the PCI/PCIe card in the PC is made by a TI TLK2711 Serializer/Deserializer chip that transfers at 2.5 GbPS:

http://www.philcovington.com/SDR/PICS/QS1RT_VERB_MED.JPG

As of October 2007, I am in the process of testing the PCI end of the interface. This board uses some expensive components and is only really meant to be a demonstration of a high speed interface and for experimentation. I want to investigate the ultimate achievable bandwidth to the PC from the VERB and also configuration of the FPGA over the high speed fiber optic link.

Quick Silver QS1R REVB

Taking what I learned from QS1R REV AB prototype and QS1RT VERB, I set about designing a third (and hopefully final!) iteration of the Quick Silver board in October 2007. In previous boards, the RF section of the PCB was routed by hand and the digital sections were done by an auto router. In QS1R REVB, all routing was done by hand to optimize trace lengths and minimize vias in the digital sections of the circuit. The board was simplified with applications such as a HF receiver, VNA, spectrum analyzer, and digital oscilloscope in mind:

http://www.philcovington.com/SDR/qs1r_10112007.pdf

http://www.philcovington.com/SDR/qs1r_revb_sch.pdf

Included on the board is a 192 kSPS Stereo DAC for audio output. There are provisions to allow an expansion BPF/RF AMP/Attenuator board, an on-board 55 MHz LPF, a direct ADC input connector that bypasses the LPF, an I2C control bus, etc… See the schematic above for details.

The QS1R REV B PCB is completed, assembled, and now undergoing testing as of October 30, 2007.

Friday, July 20, 2007

QS1RT VERB Bare PCB



(Click on picture above to see larger version)

Boards were received 07-20-2004


Thursday, July 12, 2007

QS1RT VERB PCB

QS1RT VERB (VErsatile Radio Board) Project:



(Click on picture above for a larger version)

ADC: Linear Technology LTC2208
DAC: Analog Devices AD9744
CODEC: TI TLV320AIC23B
FPGA: Altera EP3C25-QFP240 Cyclone III
CPLD: Altera EMP240-QFP100 MAX II
USB: Cypress CY7C68013A FX2
SERDES: TI TLK2701
EEPROM: Microchip 24C128

  • Internal encode clock is 125 MHz.
  • Board interface is through:
    1. USB 2.0 or,
    2. Optic Fiber SFP Module at 2.5 Gbps or,
    3. Copper Cat6 cable at 2.5 Gbps.
  • TI CODEC provides 48/96kHz audio in and audio out
  • FPGA can be programmed via USB or Fiber/Copper interface in Fast Parallel Programming mode (byte wide transfers per clock cycle).
  • JTAG interface for FPGA and CPLD
  • Connectors:
    • ADC IN
    • DAC OUT
    • EXT ENCODE IN
    • MIC IN
    • L&R AMPLIFIED AUDIO OUT
    • L&R LINE IN
    • L&R LINE OUT
    • DC POWER IN
    • JTAG
    • USB 2.0
    • RJ45 (2.5 Gbps serial over copper)
    • SFP (2.5 Gbps serial over fiber)
    • TTL Level Serial from FX2
    • SPI and I2C to RF external RF board
Status: Prototype boards are scheduled to arrive from PCB manufacturer on July 19th.

RF Front End/BPF Board:
An external RF board will determine the frequency range and will allow home-brew RF front ends. The QS1RT VERB provides an SPI and I2C bus for controlling the RF front end board.

2.5 Gbps Serial Link:
The other end of the 2.5 Gbps interface will be a PCI and PCI Express board for the PC. This interface board will have a matching TI TLK2701 SERDES, a CYCLONE II EP3C25, a TI CODEC, and a PLX PCI or PCIe-to-local bus interface chip. The two boards can be connected by Cat6 copper or optical fiber through the SFP module interface.

The USB 2.0 interface allows the use of the QS1RT VERB with PC laptops or if the copper/fiber interface is not desired.

The ADC IN and DAC OUT ports are transformer coupled using Minicircuits T1-6T transformers which gives 15 kHz to 300 MHz coverage. The external RF front end board will determine the actual frequency coverage of the system.

I am having good luck with Picolight SFP modules for the fiber interface which cost about $50 each. I have successfully tested the optical interface though 100 meters of fiber.


Wednesday, June 27, 2007

QS1RT Prototype 06272007

QS1RT:

Please click on the image to see a larger version.

Tuesday, June 19, 2007

TI PCM4222 ADC Now Available

PCM4222:

TI's 24 bit, 216 kHz, 2 channel ADC is now available. 122 dB dynamic range is claimed. The part comes in a 48 pin TQFP package. It is available from Digi-Key in single quantities at $22.42 each.

Here is the link: PCM4222

This is a FFT plot of the PCM4222 at 192 kHz with no input:


The rise in amplitude at about 65 kHz is a concern, but for SDR use a bandwidth of 130 kHz would still be useful.

The PCM4222 is definitely easier to get in single quantities for experimenters than the AKM AK5394 is, but the AKM chip is still probably the winner.



Wednesday, February 28, 2007

Quickfilter QF1D512

QF1D512

Here is a link to useful FIR engine chip:

http://www.quickfiltertech.com/html/qfilter_page.php?content_id=45

They offer a DIP version for experimentation:

http://www.quickfiltertech.com/html/qfilter_page.php?content_id=59

Mouser stocks the parts.

QS1R:

The current status is that I am working on integrating the QF1D512 part into the QS1R receiver prototype. I have no new projected availability for QS1R. In fact it appears that interest may be somewhat limited - enough so that it would not be worthwhile to offer assembled units. In that case the design files will be posted from anyone who wants to build a board.

Wednesday, January 03, 2007

QS1R Block Diagrams & Software news

QS1R Diagrams Posted:

Architecture -
PDF diagram of QS1R overall architecture

RF Front End -
PDF diagram of QS1R RF Front End

Supporting Software:

QS1R/QS1T supporting software will be an open source application called QSRunner. It will support both Windows and Linux. In addition to supporting QS1R/QS1T, QSRunner will also support the SoftRock and HPSDR JANUS-OZY/MERCURY projects.