Friday, October 28, 2005

Modified QSD Circuit

R1 represents the signal source impedance, in this case 200 ohms. If R2 is 4 x 200 ohms = 800 ohms the conversion loss is the same as a single switch with signal integrating capacitor driven by a 25% duty cycle clock. If the clock's duty cycle is increased to 50% the circuit shows some conversion gain. One side of the switch is now effectively grounded (virtual gound of the opamp). The next thing would be to investigate increasing the source impedance that each switch sees.

Below is a two switch model with LT1115 op amps:

Wednesday, October 26, 2005

QSD Simulation

Below is a plot of a model of a two switch QSD circuit. It shows voltage gain in dB vs switch on time. The input frequency is 10.005 MHz. The sampling clock period is 100 nS (10.000 MHz).

Below is a plot of a model of a four switch QSD circuit. It also shows voltage gain in dB vs switch on time. The input frequency is 10.005 MHz. The sampling clock period is 100 nS (10.000 MHz).

The model that I used can be downloaded here. You will need Linear Technology's SWCAD program to run it.

An Excel spreadsheet containing the above data can be downloaded here.

The interesting part about the above data is that the QSD seems to have the most gain when the sampling clock on time is about 20 - 25% of its period. This seems to be true in all the different models (ideal and real switches) and configurations (balanced, sinngle ended) that I have tried. Phil Harmon, VK6APH, I believe has also found this to be true in his modeling. So a 50% duty cycle clock does not seem to be beneficial.

Thursday, October 20, 2005

SharpDSP Mini Console running on Linux

Click on the picture to see a full size version

Wednesday, October 19, 2005

SharpDSP Mini Console with Analog Meter

I have added an analog meter to the SharpDSP Mini Console. I borrowed the image from meterpanel. The scale on the meter is not calibrated. You can substitute your own meter face image in place of the default image. Here are the details of the meter face image:

Size: 220 x 220 pixels
Type: png, gif, jpeg, bmp, tiff
Origin of the image is 0,0 at top - left hand corner of the image

The image file should be placed in the SharpDSPMiniConsole folder.

Here is the important part of the softrock.config.xml file relating to the meter:

  • AnalogMeterImageName is the file name of the meter face image.
  • AnalogMeterCorrection is the correction factor in dBm to apply to the analog meter reading. It defines the zero point - here it is set for -130 dBm.
  • AnalogMeterNeedleLength defines the length in pixels of the needle
  • AnalogMeterMinAngle defines the angle of the end of the needle pointer in relation to vertical (defined as needle pointing straight up - zero degrees) when the meter is at it's minimum scale reading.
  • AnalogMeterMaxAngle defines the angle of the end of the needle pointer in relation to vertical (defined as needle pointing straight up - zero degrees) when the meter is at it's maximum scale reading.
  • AnalogNeedleOrigin defines the x and y coordinates (in pixels) of the meter needle origin.
  • AnalogMeterNeedleColor defines the color of the needle in Argb units.
  • AnalogMeterNeedleWidth defines the width in pixels of the needle.
To create your own meter face you need to keep the image size to 220 x 220 pixels. You will need to note where the needle origin is on your image in pixel units with 0,0 being located at the top - left hand side of the image. You will also have to set the minimum and maximum angles for the needle to define the zero and full scale positions in your image.

The default vu meter face that comes with the SharpDSP Mini Console is not calibrated.

Wednesday, October 12, 2005

Some notes on the SharpDSP Mini Console...

SharpDSP Mini Console for the SoftRock:

It is available on my website at

Center Frequency Calibration Procedure:

The SharpDSP Mini Console allows you to set any desired center frequency. For the standard SoftRock 40 the center frequency is 7.056 Mhz. To get an accurate frequency display you will need to calibrate this setting. Here is how I did it:

I set my HP8640B signal generator to 7040 kHz. I moved the low filter slider to -2000 Hz and the high filter slider to +2000 Hz. I then selected SSB/DSB/CW from the Mode menu. I then moved the frequency tuning slider until I got zero beat on the 7040 kHz signal. This occurred around 7046 kHz on my SoftRock 40. I then clicked on the Setup->Center Freq menu. The text box showed that the software was set for a center frequency of 7056 kHz (7056000). Using the fine tuning slider I adjusted the displayed frequency (at the bottom of the screen above the frequency tuning slider) until it read 7040000 - exactly what the HP8640B was set to. When you move the fine tuning adjustment slider you will also see that it is changing the displayed center frequency in the text box above it by the amount corrected to get the display to show 7040 kHz. I then clicked on the Done button to accept the new center frequency. The calibration is done.

Here is what that screen looks like. You can see my new calibrated center frequency setting.

IQ Balance procedure (Image Rejection):

To calibrate the image rejection setting I left the HP8640B set to 7040 kHz. I then tuned up with the frequency slider until I could hear the image. This occurs at 7072 kHz if your center frequency is 7056 kHz (7056 - 7040 = 16, so 7056 + 16 = 7072). I then clicked on the Levels->Correction menu. I adjusted first the IQ Gain Correction slider for a decrease in the image signal. I then adjusted the IQ Phase Correction slider for a decrease. I went back and forth between the two sliders until I nulled the signal as low as possible. I then clicked Done to exit this screen:

Meter Level Calibration Procedure:

To set the meter level I adjusted the HP8640B to -70 dbm on 7040 kHz. I then clicked on the Levels->Correction menu again. You will see that the s-meter is still visible on this form. This is to aide in calibration. To adjust the s-meter to read -70 dbm I just moved the Signal Level Correction slider until the s-meter read -70 dbm. I then clicked Done.

Hint: You can move the sliders in very small steps by making sure the slider has the focus and then using the left and right arrows on the keyboard. You can also move in slightly larger steps by left clicking to the right or left of the slider.

Thursday, October 06, 2005

Additional info on the HPSDR project...

Hi all,

This is a response to a few questions that someone posted on my blog
page requesting more info about the project. I have copied it here
since it kind of gives a quick outline of where I am going:

I saw your comment on my blog page. Thanks for the link.

I am using libusb-win32 which is a port of the open source libusb
project for Linux. My intention is to use the libusb API since it is
the same on Windows as it is on Linux. On Windows is consists of a
device driver and a interface DLL. They have an inf file generator
that will create an .inf file for your device. I am having very good
luck with libusb.

I have written a C#.NET library to interface to the libusb-win32 DLL.
It works under the Mono framework in both Windows (using the
libusb-win32 driver and DLL) and Linux (using the libusb shared
library). It is pretty cool to be able to write software and have it
work without recompiling on both Win and Linux platforms.

For the compiler I want to use the open source SDCC compiler. It
assumes a standard 8051 type device so it does not directly support
the additional features of the FX2. Basically I have to create custom
interrupt vector and usb descriptor tables in assembly modules and
link them with the main c firmware. Luckily the SDCC linker allows
you to define where in memory particular user defined segments are
based so it turned out to be relatively easy one I pieced together all
the bits of information from various sources on the internet.

The only problem that I am having now is that I cannot get the
SUDPTR's (that you use to send the usb configuration descriptors) to
work. I load them with the correct address but invalid data is
returned. I think that there is a problem with the xdata
initialization in SDCC's startup code because it assumes a standard
8051. I am working on a replacement .startup8051.asm for the FX2 to
correct the deficiencies. The device will not re-enumerate correctly
because of the SUDPTR problem. [Edit: As of 10-05-2005 this problem
has been resolved and the board re-enumerates correctly - N8VB]

Once I get the re-enumeration fixed, I need to complete the firmware
to support uploading the FPGA's configuration data.

I apologize for not responding to your earlier comment on my blog
about having a block diagram for the FPGA_USB board. I just saw your
message today - I guess I missed it. I've been busy in every spare
moment writing support code and firmware for the FPGA_USB board that I
have not released much info on it. Basically the FPGA_USB board is a
high speed I/O system. It has an I2C bus, an SPI bus, and about 64
lines of bit addressable I/O. It has six 40 pin header receptacles on
the board to allow interfacing. The I2C and SPI buses are common to
five of the six headers. The remaining pins on the first five headers
also contain power and GP I/O lines that can be configured either for
CS or ENs for the SPI bus or as general purpose bit addressable I/O.
The first and third headers also have individual I2S sound buses to
allow connection to the audio A/Ds and D/As. If the I2S buses are not
needed those lines can be reconfigured as GP I/O by the FPGA. The
sixth header contains all bit addressable GP I/O that is not common to
the first five headers. The plug in boards will make the project a
SDR, test instrument, etc... For SDR use I plan on having a RX board
(with PCM4202 A/D) in the first slot, a DDS board in the second slot,
a TX board (with A/D - D/A) in the third slot, a BPF board in the
fourth slot, and general purpose I/O interface board in the fifth
slot. I want to use a mini-itx board running Linux that will
interface via USB to the FPGA_USB board and allow you to make a stand
alone radio. The GP I/O will be used for interface to the front panel
encoder knobs, switches, indicators, etc... It will also support
running in PC connected mode like the SDR-1000 with or without the
mini-itx board. I would like to offload some of the DSP to the FPGA
also (like the I/Q correction and NCO for starters). I am very
interested in some of the open cores for the FPGAs that implement your
own custom DSP processor. It would be interesting to see if all the
DSP could be done in the FPGA or in maybe a add on FGPA based
co-processor board.

If I ever get all the above done I would then like to make a high
speed 16 bit A/D board that would replace the TX board and allow you
to scan a large swath of spectrum. Then the narrow bandwidth RX board
(using the QSD and audio A/D) would tune into interesting signals. I
have a sample of a 16 bit 80MSPS A/D from Analog Devices that I will
use. The same board could also be the basis for a high speed DSO or
logic analyzer project.

The inspiration for the FPGA_USB board was to have an expandable high
speed I/O platform to build other projects on. In addition to the FX2
and Spartan 3 FPGA there is a 128 K static ram for the FX2, a 64 K
EEPROM, a Cypress I2C programmable clock generator chip with 6 clock
outputs, and regulators (3.3V, 2.5V, and 1.2V). The board requires 5V
for the logic and +/- 12 VDC for supporting the add on boards. The
+/- 12 V supplies are routed directly to the six headers.

Anyway, it is all a lot of fun!

73 de Phil N8VB