HPSDR and XYLO SDR group combine

HPSDR PROJECT:
We have combined the HPSDR and XYLO SDR groups into one project with common goals. There is a new domain and website for the project:

http://hpsdr.org

The XYLO SDR mailing list has now become the HPSDR mailing list. To join the list go to:

http://hpsdr.org/reflector.html

ATLAS BUS:

This is the first attempt at defining the physical layout of the Atlas bus.

The board ended up being 5.500" x 3.940", six slots, and 4 layers with
the following stackup:

1. Ground Plane (top component side)
2. YBUS
3. Power Plane (+12,-12, +5, -5, +3.3)
4. XBUS (bottom side)

Details are in the following document:

http://www.philcovington.com/HPSDR/ATLAS/Atlas_doc.pdf

After reading the document there are some other pdfs (such as the
schematic) in this folder:

http://www.philcovington.com/HPSDR/ATLAS/

For those interested, I'd appreciate if you'd please take a look at
the documents and make questions/comments.

Comments

History of HPSDR Mercury and Quick Silver

History of HPSDR Mercury and Quick Silver Philip Covington, N8VB Early HPSDR and XYLO In 2005 I started a High Performance SDR (HPSDR) project which was to consist of a motherboard carrying a FPGA/USB 2.0 interface and power supply with the provision for plug in modules through 40 pin headers. I had planned a narrow band high dynamic range module based on a QSD/DDS/PCM4202 audio ADC and a wide bandwidth module based on a high speed 16 bit ADC: http://www.philcovington.com/SDR/PICS/HPSDR_FPGA_USB_Board_top1_800600.jpg http://www.philcovington.com/SDR/PICS/HPSDR_FPGA_USB_Board_top4.jpg I soon selected the LTC2208 ADC from Linear Technology. A representative from Linear Technology came across my blog ( http://pcovington.blogspot.com/ ) and offered evaluation boards and samples to support the project. At about the same time my HPSDR project came about, Phil Harman, VK6APH and Bill Tracey, KD5TFD were interested developing a sound card replacement to be used with the SD

QuickSilver QS1R Software Defined Receiver Prototype

QS1R Software Defined Receiver: (Click on picture above for larger version.) Features: 16 bit 130 MSPS ADC HPF, LPF, RF AMP Switchable Front End 0-31.5 dB Attenuator in 0.5 dB steps Cyclone II FPGA Two AD6620 DDC co-processors USB 2.0 480 Mbps High Speed Interface to PC 0.1 to 33 MHz coverage (0.1 to 65 MHz extended) RX bandwidths from 33 MHz to 1kHz Two independent RX channels anywhere in 0.1 to 33 MHz 6.00" X 4.00" board size Single +12V 1A supply Open Source Software and Hardware Availability: Projected late January to mid-February 2007

Philip A Covington’s Blog

Search This Blog