Skip to main content

Update... HPSDR

HPSDR Progress:
I am now able to configure the Spartan 3 FPGA over USB. I switched from slave parallel mode to slave serial configuration loading. This will make the FX2 firmware easy to use with Altera Cyclone FPGAs in addition the the Xilinx Spartan 3.

I am in the process of getting samples of Linear Technology's LTC2208 16 bit, 135 MSPS ADC. I still plan to develop a QSD based RX board using the TI PCM4202 as the ADC - So there will be a high bandwidth path as well as a low bandwidth path in the HPSDR. The LTC2208 board will probably get it's own FPGA to do DDC. The DDC's ouput will then feed the Spartan 3 which will be responsible for performing the second part of the DSP chain.

Verilog Projects for the Xylo Board:
I set up a folder on my server that people can browse . It will contain various verilog projects that can be tried on the Xylo board for educational purposes.

http://www.philcovington.com/FPGA/

Comments

Anonymous said…
I have pretty much used VHDL, and feel more comfortable with it.

Whay was Verilog chosen? was it because it looks a lot like C/C++/C#?

I just would like to know...
Phil Covington said…
Let me ask you why have you chosen to use VHDL over Verilog?

N8VB

Popular posts from this blog

History of HPSDR Mercury and Quick Silver

History of HPSDR Mercury and Quick Silver Philip Covington, N8VB Early HPSDR and XYLO In 2005 I started a High Performance SDR (HPSDR) project which was to consist of a motherboard carrying a FPGA/USB 2.0 interface and power supply with the provision for plug in modules through 40 pin headers. I had planned a narrow band high dynamic range module based on a QSD/DDS/PCM4202 audio ADC and a wide bandwidth module based on a high speed 16 bit ADC: http://www.philcovington.com/SDR/PICS/HPSDR_FPGA_USB_Board_top1_800600.jpg http://www.philcovington.com/SDR/PICS/HPSDR_FPGA_USB_Board_top4.jpg I soon selected the LTC2208 ADC from Linear Technology. A representative from Linear Technology came across my blog ( http://pcovington.blogspot.com/ ) and offered evaluation boards and samples to support the project. At about the same time my HPSDR project came about, Phil Harman, VK6APH and Bill Tracey, KD5TFD were interested developing a sound card replacement to be used with the SD

QuickSilver QS1R Software Defined Receiver Prototype

QS1R Software Defined Receiver: (Click on picture above for larger version.) Features: 16 bit 130 MSPS ADC HPF, LPF, RF AMP Switchable Front End 0-31.5 dB Attenuator in 0.5 dB steps Cyclone II FPGA Two AD6620 DDC co-processors USB 2.0 480 Mbps High Speed Interface to PC 0.1 to 33 MHz coverage (0.1 to 65 MHz extended) RX bandwidths from 33 MHz to 1kHz Two independent RX channels anywhere in 0.1 to 33 MHz 6.00" X 4.00" board size Single +12V 1A supply Open Source Software and Hardware Availability: Projected late January to mid-February 2007

2323 Wilt