QS1R Software Defined Receiver:
(Click on picture above for larger version.)
Features:
16 bit 130 MSPS ADC
HPF, LPF, RF AMP Switchable Front End
0-31.5 dB Attenuator in 0.5 dB steps
Cyclone II FPGA
Two AD6620 DDC co-processors
USB 2.0 480 Mbps High Speed Interface to PC
0.1 to 33 MHz coverage (0.1 to 65 MHz extended)
RX bandwidths from 33 MHz to 1kHz
Two independent RX channels anywhere in 0.1 to 33 MHz
6.00" X 4.00" board size
Single +12V 1A supply
Open Source Software and Hardware
Availability:
Projected late January to mid-February 2007
(Click on picture above for larger version.)
Features:
16 bit 130 MSPS ADC
HPF, LPF, RF AMP Switchable Front End
0-31.5 dB Attenuator in 0.5 dB steps
Cyclone II FPGA
Two AD6620 DDC co-processors
USB 2.0 480 Mbps High Speed Interface to PC
0.1 to 33 MHz coverage (0.1 to 65 MHz extended)
RX bandwidths from 33 MHz to 1kHz
Two independent RX channels anywhere in 0.1 to 33 MHz
6.00" X 4.00" board size
Single +12V 1A supply
Open Source Software and Hardware
Availability:
Projected late January to mid-February 2007
Comments
Larry K2LT
I'll post more information on pricing and availability very soon. I'll probably create an "interest" list to get an idea of how many units to do for a first run.
73 de Phil N8VB
[Will it be possible to phase lock the 2 receivers?]
Yes, there is provision for external encode clock input to drive multiple boards and the board was designed with that in mind. The AD6620 DDC chips also have sync capability.
73 de Phil N8VB
Terry, WB4JFI
Any thought of using a QS1R as a 'scope?
Put me down for one as well please
Larry, VE6VQ/W7
I am interested, so keep me in the loop.
Mike G0MJW
The QS1R will cost what it costs and the cost is yet to be determined. The most expensive component is the LTC2208 ADC.
Phil N8VB
I'm interested, please keep me in the loop.
thanks, rob
I am intrested in at least one.
Thanks
AL KE5EUP