A SDR based on some K2 design ideas

Here is a diagram of a SDR that uses ideas from the K2 RF front end and PLL synthesizer:

K2LikeSDR.pdf

It would use the K2's RF front end. I would substitute the TUF-1 mixer of the K2 with a switching mixer based on a FST3125 bus switch. The QSD would be at a fixed IF of 5 MHz. The LO for the QSD would be derived from a fixed 20 MHz oscillator divided by 4 to generate the quadrature signals needed to driver the QSD switches. The K2's PLL would be modified by eliminating the variable reference oscillator (resulting in the PLL tuning in 5 kHz steps) and substituting one of the LMX National PLLs for the MC145170 PLL used in the K2 design. The K2's VCO design is good, but I would also eliminate the VCO AGC circuit of the K2.

Comments

Anonymous said…

The K2 is a good choice for experimenting. It is e.g. very well possible to couple two K2 frontends and make them phase coherent. Using the SSB-filter module I/Q processing is not needed. See: http://www.pa0sim.nl/Hardware.htm
All the processing is done in the software.

73 Jan PA0SIM

3:48 AM

Gian I7SWX said…

Hi Phil,

I do agree 100% with you on the K2 SDR idea. The 2T H-Mode Mixer with FST3125 has been already applied as a mod to replace the TUF1 mixer giving a very high IP3 improvement. Having a strong front end conversion followed by the classic QSD with FST3125 will certainly be appreciated by HF people and give a distance to many commercial receivers.
Although the TUF replacement with the H-Mode Mixer is a 1 to 1 job, I can deliver all info on this mode.

73

Gian
I7SWX
I can del

12:25 PM

History of HPSDR Mercury and Quick Silver

History of HPSDR Mercury and Quick Silver Philip Covington, N8VB Early HPSDR and XYLO In 2005 I started a High Performance SDR (HPSDR) project which was to consist of a motherboard carrying a FPGA/USB 2.0 interface and power supply with the provision for plug in modules through 40 pin headers. I had planned a narrow band high dynamic range module based on a QSD/DDS/PCM4202 audio ADC and a wide bandwidth module based on a high speed 16 bit ADC: http://www.philcovington.com/SDR/PICS/HPSDR_FPGA_USB_Board_top1_800600.jpg http://www.philcovington.com/SDR/PICS/HPSDR_FPGA_USB_Board_top4.jpg I soon selected the LTC2208 ADC from Linear Technology. A representative from Linear Technology came across my blog ( http://pcovington.blogspot.com/ ) and offered evaluation boards and samples to support the project. At about the same time my HPSDR project came about, Phil Harman, VK6APH and Bill Tracey, KD5TFD were interested developing a sound card replacement to be used with the SD

2323 Wilt

Possible QSD/ISD Switches/ ADC Idea/Misc

QSD/ISD Switches: Here is a link the PDF data sheets of analog switches that can be investigated for use in QSD/ISD circuits: http://www.philcovington.com/HPSDR/QSD_SWITCH/ Interesting ADC: Here is a link to an interesting ADC by Analog Devices: http://www.analog.com/UploadedFiles/Data_Sheets/AD7760.pdf It is a 24 bit, 2.5 MSPS ADC. Here is the circuit idea: http://www.philcovington.com/HPSDR/TEMP_STUFF/AD7760QSD.pdf It uses 1/2 of a QSD (not quadrature sampled) to mix the frequency band of interest down to zero Hz with a bandwidth of something like 250 kHz. The IF would be offset to something like 125 kHz. The ADC samples the 1/2QSD output and results in a real data stream. A FPGA or CPLD mixes the real data stream with a complex NCO to generate a quadrature data stream which is sent over USB to the PC where the remaining processing is done. The advantage is a 1 X LO and no I/Q balance problems. One disadvantage is that your sampling rate should be 4 times the desired bandwidth

Philip A Covington’s Blog

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