QS1R Software Defined Receiver: (Click on picture above for larger version.) Features: 16 bit 130 MSPS ADC HPF, LPF, RF AMP Switchable Front End 0-31.5 dB Attenuator in 0.5 dB steps Cyclone II FPGA Two AD6620 DDC co-processors USB 2.0 480 Mbps High Speed Interface to PC 0.1 to 33 MHz coverage (0.1 to 65 MHz extended) RX bandwidths from 33 MHz to 1kHz Two independent RX channels anywhere in 0.1 to 33 MHz 6.00" X 4.00" board size Single +12V 1A supply Open Source Software and Hardware Availability: Projected late January to mid-February 2007
Here I will post information about the current status of SRL-LLC projects and other general SDR information. SRL-LLC website: www.srl-llc.com
Comments
Looks very very good indeed!!
Was this wave soldered or manually(hand soldered)?
Look forward to hear next stage and have a go at a kit in due course.
Jan G0BBL
congratulations
Just finished Closely examining QS1RT Soldered and recalling our last May telecom. The board is simply fascinating.
I'll be talking to you soon!
With kindest regards,
Juan