Wednesday, July 27, 2005

SDR mini-itx project update

Here is an update on my mini-itx/SDR project:

I have been working out the details of the A/D – D/A board. I have decided to use the TI PCM4202 (24 bit, 192 kHz, stereo) for the RX A/D. For the TX A/D and RX/TX D/A I am going to use the TI TLV320AIC23B CODEC (24 bits, 8-98 kHz, stereo, with integrated mic amp and headphone driver). The PCM4204 will be dedicated to RX only. The TLV320AIC23B will handle the microphone input for TX as well as the IQ output for TX and the audio output for RX (in the stand alone configuration).

Both chips have digital audio interfaces (I2S, left, right justified, etc…) so I have the problem of getting that data into the PC via USB2.0. I looked at the Cypress EZ-USB FX2 CY7C68013 microcontroller for this but it cannot handle the transfer on its own. I decided to use a Xilinx FPGA in addition to the EZ USB FX2 for the I2S to parallel conversion (inspired by the USRP and SSRP projects of GnuRadio). The EZ USB FX2 will operate in slave FIFO mode to get the data/to from USB2.0. It seems a shame to waste all the I/O available with the FPGA so there will be general purpose parallel I/O, I2C, and SPI bus capability for future expansion*. In addition, since I already have the SPI/Microwire bus, I want to provide the ability to interface two AD9954 DDS chips to the FPGA. The AD9954 has a few dedicated I/O pins for synchronization between multiple chips as well as built in comparators that make it easy to generate a quadrature IQ clock up to 160 Mhz. The AD9954 has a 14 bit D/A so there should be less spurs.

The interface to the PCM4202 requires the digital audio interface lines (LRCK, BCK, DATA) and 3 sample rate select lines. The TLV320AIC23B requires the digital audio interface lines (LRCK, BCK, DIN, DOUT) and 3 wire SPI lines (for control) + /CS. The AD9954 requires 3 wire SPI lines for control and a /CS line. The SPI bus lines will be shared between the TLV320AIC23B and the two AD9954 DDS chips requiring 3 /CS lines, one for each chip.

Part of the parallel I/O will interface to the parallel connector on the SDR-1000 and the rest will be available for user defined I/O.

I will post more on my website as I make progress. Any input, suggestions, and criticisms are welcome.

Phil

*future expansion = high speed ( >=50MSPS) 14 bit A/D

1 comment:

Bob N4HY said...

Phil:

This is very interesting work. I really like the idea of marrying the Mini-ITX to the FPGA hardware to make a completely standalong system. Have you decide on distribution for this work as in hardware (build boards, kits, bare boards)? As the new AMSAT VP Eng., I am looking for ground station hardware for a major digital communications experiment we are attempting on the AMSAT Eagle spacecraft. I am also interested in using a network of devices such as you are building to do some jobs for my employer and sponsor. An important consideration in the latter would be the ability to lock all clocks involved in the signal processing to a single reference.

Great stuff!
Bob