Thursday, October 06, 2005
Additional info on the HPSDR project...
This is a response to a few questions that someone posted on my blog
page requesting more info about the project. I have copied it here
since it kind of gives a quick outline of where I am going:
I saw your comment on my blog page. Thanks for the link.
I am using libusb-win32 which is a port of the open source libusb
project for Linux. My intention is to use the libusb API since it is
the same on Windows as it is on Linux. On Windows is consists of a
device driver and a interface DLL. They have an inf file generator
that will create an .inf file for your device. I am having very good
luck with libusb.
I have written a C#.NET library to interface to the libusb-win32 DLL.
It works under the Mono framework in both Windows (using the
libusb-win32 driver and DLL) and Linux (using the libusb shared
library). It is pretty cool to be able to write software and have it
work without recompiling on both Win and Linux platforms.
For the compiler I want to use the open source SDCC compiler. It
assumes a standard 8051 type device so it does not directly support
the additional features of the FX2. Basically I have to create custom
interrupt vector and usb descriptor tables in assembly modules and
link them with the main c firmware. Luckily the SDCC linker allows
you to define where in memory particular user defined segments are
based so it turned out to be relatively easy one I pieced together all
the bits of information from various sources on the internet.
The only problem that I am having now is that I cannot get the
SUDPTR's (that you use to send the usb configuration descriptors) to
work. I load them with the correct address but invalid data is
returned. I think that there is a problem with the xdata
initialization in SDCC's startup code because it assumes a standard
8051. I am working on a replacement .startup8051.asm for the FX2 to
correct the deficiencies. The device will not re-enumerate correctly
because of the SUDPTR problem. [Edit: As of 10-05-2005 this problem
has been resolved and the board re-enumerates correctly - N8VB]
Once I get the re-enumeration fixed, I need to complete the firmware
to support uploading the FPGA's configuration data.
I apologize for not responding to your earlier comment on my blog
about having a block diagram for the FPGA_USB board. I just saw your
message today - I guess I missed it. I've been busy in every spare
moment writing support code and firmware for the FPGA_USB board that I
have not released much info on it. Basically the FPGA_USB board is a
high speed I/O system. It has an I2C bus, an SPI bus, and about 64
lines of bit addressable I/O. It has six 40 pin header receptacles on
the board to allow interfacing. The I2C and SPI buses are common to
five of the six headers. The remaining pins on the first five headers
also contain power and GP I/O lines that can be configured either for
CS or ENs for the SPI bus or as general purpose bit addressable I/O.
The first and third headers also have individual I2S sound buses to
allow connection to the audio A/Ds and D/As. If the I2S buses are not
needed those lines can be reconfigured as GP I/O by the FPGA. The
sixth header contains all bit addressable GP I/O that is not common to
the first five headers. The plug in boards will make the project a
SDR, test instrument, etc... For SDR use I plan on having a RX board
(with PCM4202 A/D) in the first slot, a DDS board in the second slot,
a TX board (with A/D - D/A) in the third slot, a BPF board in the
fourth slot, and general purpose I/O interface board in the fifth
slot. I want to use a mini-itx board running Linux that will
interface via USB to the FPGA_USB board and allow you to make a stand
alone radio. The GP I/O will be used for interface to the front panel
encoder knobs, switches, indicators, etc... It will also support
running in PC connected mode like the SDR-1000 with or without the
mini-itx board. I would like to offload some of the DSP to the FPGA
also (like the I/Q correction and NCO for starters). I am very
interested in some of the open cores for the FPGAs that implement your
own custom DSP processor. It would be interesting to see if all the
DSP could be done in the FPGA or in maybe a add on FGPA based
If I ever get all the above done I would then like to make a high
speed 16 bit A/D board that would replace the TX board and allow you
to scan a large swath of spectrum. Then the narrow bandwidth RX board
(using the QSD and audio A/D) would tune into interesting signals. I
have a sample of a 16 bit 80MSPS A/D from Analog Devices that I will
use. The same board could also be the basis for a high speed DSO or
logic analyzer project.
The inspiration for the FPGA_USB board was to have an expandable high
speed I/O platform to build other projects on. In addition to the FX2
and Spartan 3 FPGA there is a 128 K static ram for the FX2, a 64 K
EEPROM, a Cypress I2C programmable clock generator chip with 6 clock
outputs, and regulators (3.3V, 2.5V, and 1.2V). The board requires 5V
for the logic and +/- 12 VDC for supporting the add on boards. The
+/- 12 V supplies are routed directly to the six headers.
Anyway, it is all a lot of fun!
73 de Phil N8VB
Posted by Phil Covington at 11:53 AM