Wednesday, October 26, 2005

QSD Simulation

Below is a plot of a model of a two switch QSD circuit. It shows voltage gain in dB vs switch on time. The input frequency is 10.005 MHz. The sampling clock period is 100 nS (10.000 MHz).





Below is a plot of a model of a four switch QSD circuit. It also shows voltage gain in dB vs switch on time. The input frequency is 10.005 MHz. The sampling clock period is 100 nS (10.000 MHz).



The model that I used can be downloaded here. You will need Linear Technology's SWCAD program to run it.

An Excel spreadsheet containing the above data can be downloaded here.

The interesting part about the above data is that the QSD seems to have the most gain when the sampling clock on time is about 20 - 25% of its period. This seems to be true in all the different models (ideal and real switches) and configurations (balanced, sinngle ended) that I have tried. Phil Harmon, VK6APH, I believe has also found this to be true in his modeling. So a 50% duty cycle clock does not seem to be beneficial.

4 comments:

Anonymous said...

Phil,
I see that in your four switch QSD, the opamp inverting input impedance is 10k (minus input is a virtual ground) and non-inverting input impedance is 20k from the two series 10k resistors (plus input is high impedance), resulting in gain inbalance.
In a complete QSD, the other 2 outputs and other opamp would balance things up, but I wonder if the different RC discharge constants play any detrimental effect.

Anonymous said...

Oops, anonymous is JK De Marco, PY2WM

Phil Covington said...

The circuit is only for experimentation and modeling. I am not proposing that anyone use the particular circuit in the simulation for a real work receiver. If you remove the opamp altogether, it makes no difference in the thing I was trying to investigate - the clock duty cycle.

73 de Phil N8VB

Dan, N7VE said...

The roll off on the high end simply shows the effect of integrating over a larger and larger fraction of RF sine wave period.

At 25 nsec, one quarter of a RF cycle, the average of the incoming RF pulses is 0.9x of the peak. This should give 1 db of peak voltage loss

At 50 nsec, one half of a RF cycle, the average of the incoming RF pulses should be 0.707x the peak voltage or 3 db of peak voltage loss.

Going larger than 50 nsec, half an RF cycle will start averaging the positive half of the cycle with some of the negative half, thus loss will continue to increase until you get to 100 nsec, at which point you will be averaging an entire RF cycle, which should have an average of zero.

Continuing past 100 nsec, you will start seeing the response to the third harmonic.

These results look in general as expected. The main interesting point is the falling off of the response as the capture region is made a lot shorter than a quarter cycle or 25 nsec. When viewed from the charge integration point of view, the shorter the pulse, the closer the peak voltage ought to get to 1x the peak input voltage.

You might see that effect better if a detection cap were included. I am not sure how the op-amps will react well to this.

In general, I have tried modeling a normal 4:1 Tayloe detector in LT spice and found that the op-amps did not behave as expected when using the differential voltages formed across the detection caps. I would be a bit wary in reading to much into LT Spice results for this kind of circuit. I think the problem might be that we are looking at a time continuous series of events in the real world, and LT Spice is actually modeling this using discrete time steps, which seem to introduce some noticeable simulation errors in this kind of circuit.