Some Interesting Links for Decemeber...

Links

DSPLINKS - great for learning DSP interactively

QUCS- circuit simulator for Linux and Windows

LTC SWCAD - circuit simulator for Windows

Cell Processor - the processor that power the PS3

SciLab- open source numerical computation

Maxima - open source computer algebra system

Octave - open source GNU numerical computation

Mono - open source .NET

Coming Soon!

QuickSilver QS1R SDR Receiver/Scope/Spectrum Analyzer Board

Based on Linear Technology LTC2208 130 MSPS 16 bit ADC
Cyclone II EP2C8 FPGA for DDC processor
High Speed USB 2.0 Connectivity
Two DDC Co-processors
External Clocking capability
6.00" x 4.00" (15.24 x 10.16 cm) board size
0.1-65 MHz
Open Source Software

Comments

History of HPSDR Mercury and Quick Silver

History of HPSDR Mercury and Quick Silver Philip Covington, N8VB Early HPSDR and XYLO In 2005 I started a High Performance SDR (HPSDR) project which was to consist of a motherboard carrying a FPGA/USB 2.0 interface and power supply with the provision for plug in modules through 40 pin headers. I had planned a narrow band high dynamic range module based on a QSD/DDS/PCM4202 audio ADC and a wide bandwidth module based on a high speed 16 bit ADC: http://www.philcovington.com/SDR/PICS/HPSDR_FPGA_USB_Board_top1_800600.jpg http://www.philcovington.com/SDR/PICS/HPSDR_FPGA_USB_Board_top4.jpg I soon selected the LTC2208 ADC from Linear Technology. A representative from Linear Technology came across my blog ( http://pcovington.blogspot.com/ ) and offered evaluation boards and samples to support the project. At about the same time my HPSDR project came about, Phil Harman, VK6APH and Bill Tracey, KD5TFD were interested developing a sound card replacement to be used with the SD

2323 Wilt

Possible QSD/ISD Switches/ ADC Idea/Misc

QSD/ISD Switches: Here is a link the PDF data sheets of analog switches that can be investigated for use in QSD/ISD circuits: http://www.philcovington.com/HPSDR/QSD_SWITCH/ Interesting ADC: Here is a link to an interesting ADC by Analog Devices: http://www.analog.com/UploadedFiles/Data_Sheets/AD7760.pdf It is a 24 bit, 2.5 MSPS ADC. Here is the circuit idea: http://www.philcovington.com/HPSDR/TEMP_STUFF/AD7760QSD.pdf It uses 1/2 of a QSD (not quadrature sampled) to mix the frequency band of interest down to zero Hz with a bandwidth of something like 250 kHz. The IF would be offset to something like 125 kHz. The ADC samples the 1/2QSD output and results in a real data stream. A FPGA or CPLD mixes the real data stream with a complex NCO to generate a quadrature data stream which is sent over USB to the PC where the remaining processing is done. The advantage is a 1 X LO and no I/Q balance problems. One disadvantage is that your sampling rate should be 4 times the desired bandwidth

Philip A Covington’s Blog

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