Philip A Covington’s Blog

QF1D512 Here is a link to useful FIR engine chip: http://www.quickfiltertech.com/html/qfilter_page.php?content_id=45 They offer a DIP version for experimentation: http://www.quickfiltertech.com/html/qfilter_page.php?content_id=59 Mouser stocks the parts. QS1R: The current status is that I am working on integrating the QF1D512 part into the QS1R receiver prototype. I have no new projected availability for QS1R. In fact it appears that interest may be somewhat limited - enough so that it would not be worthwhile to offer assembled units. In that case the design files will be posted from anyone who wants to build a board.

QS1R Diagrams Posted: Architecture - PDF diagram of QS1R overall architecture RF Front End - PDF diagram of QS1R RF Front End Supporting Software: QS1R/QS1T supporting software will be an open source application called QSRunner. It will support both Windows and Linux. In addition to supporting QS1R/QS1T, QSRunner will also support the SoftRock and HPSDR JANUS-OZY/MERCURY projects.

QS1R Software Defined Receiver: (Click on picture above for larger version.) Features: 16 bit 130 MSPS ADC HPF, LPF, RF AMP Switchable Front End 0-31.5 dB Attenuator in 0.5 dB steps Cyclone II FPGA Two AD6620 DDC co-processors USB 2.0 480 Mbps High Speed Interface to PC 0.1 to 33 MHz coverage (0.1 to 65 MHz extended) RX bandwidths from 33 MHz to 1kHz Two independent RX channels anywhere in 0.1 to 33 MHz 6.00" X 4.00" board size Single +12V 1A supply Open Source Software and Hardware Availability: Projected late January to mid-February 2007

vSound Status I have been able to get a prototype of the vSound driver to work on Windows Vista beta. I am now waiting until the official release of Vista to continue development on a driver that will work on both XP and Vista. As it looks now, vSound will support Vista and XP only. There will be no support for W2K, NT4, or Win9X/ME operating systems. My main concern is trying to make sure that the vSound driver is compatible with both XP and Vista so I don't have to maintain two different versions based on operating system. There are a lot of changes being made to driver development under Windows and I have been waiting until it stabilizes a little bit more before releasing a beta driver. My best estimate for availability of vSound beta is early next year after Vista systems hit the streets. New QuickSilver QS1R Group Support and discussion group for the new QuickSilver QS1R SDR: To sign up go Here

Links DSPLINKS - great for learning DSP interactively QUCS - circuit simulator for Linux and Windows LTC SWCAD - circuit simulator for Windows Cell Processor - the processor that power the PS3 SciLab - open source numerical computation Maxima - open source computer algebra system Octave - open source GNU numerical computation Mono - open source .NET Coming Soon! QuickSilver QS1R SDR Receiver/Scope/Spectrum Analyzer Board Based on Linear Technology LTC2208 130 MSPS 16 bit ADC Cyclone II EP2C8 FPGA for DDC processor High Speed USB 2.0 Connectivity Two DDC Co-processors External Clocking capability 6.00" x 4.00" (15.24 x 10.16 cm) board size 0.1-65 MHz Open Source Software

Here is a diagram of a SDR that uses ideas from the K2 RF front end and PLL synthesizer: K2LikeSDR.pdf It would use the K2's RF front end. I would substitute the TUF-1 mixer of the K2 with a switching mixer based on a FST3125 bus switch. The QSD would be at a fixed IF of 5 MHz. The LO for the QSD would be derived from a fixed 20 MHz oscillator divided by 4 to generate the quadrature signals needed to driver the QSD switches. The K2's PLL would be modified by eliminating the variable reference oscillator (resulting in the PLL tuning in 5 kHz steps) and substituting one of the LMX National PLLs for the MC145170 PLL used in the K2 design. The K2's VCO design is good, but I would also eliminate the VCO AGC circuit of the K2.

SDR LO Ideas: There has been a lot of discussion of using DDS or PLLs for the LO generation for HPSDR and SoftRock like receivers. In the current SoftRock series the LO is generated by a crystal oscillator. The downsides of the above approaches are: 1. DDS: spurs and cost of a decent low jitter/low noise clock source. Some of the 400 and 500 MHz DDS chips are on the expensive side. 2. PLL: phase noise. A scheme using a microwave VCO/PLL and dividing it down into the HF range has been discussed. The latest feeling is that the phase noise reduction even after dividing down is not enough to provide a high performance system. A dual PLL loop approach has been proposed to improve phase noise performance but it is likely to be expensive. There are also PLL/DDS approaches of varying complexity. 3. Xtal: limited frequency agility, you are limited to tuning within the passband of your computer sound card. There is a forth method that might work for lower cost SDR circuits like the SoftR...